With reference to FIG. 1 we briefly describe the operation of a typical prior art electronics-based multiplexer/demultiplexer circuit. Each input (e.g., A) consists of an elastic buffer (e.g., 101) and a clock recovery circuit (e.g., 103). The clock recovery circuit extracts clock C1 from the input data signal and uses it to clock the data into elastic buffer 101. This data is then clocked out of the elastic buffer with a local clock C2, sampled by the multiplexer 105 and transmitted over communication link 107. At demultiplexer 113, the clock C1 is recovered by circuit 109 from the transmitted signal and used to clock the data into elastic buffer 111. A local clock C3 synchronized with demultiplexer 113 is used to clock the data from elastic buffer 111 to demultiplexer 113. Additionally, multiplexers 105 and 113 have to be synchronized.
Such electronic multiplexer/demultiplexer circuits usually have to be adapted to accommodate the data rate of a variety of continuous or packet input data rates by adjusting the size of the elastic buffers, as long as the data clock rate C2 is greater than the long term average data rate of input A. As input data rates increase and/or communication link data rates change, the multiplexer/demultiplexer may have to be adapted or redesigned and clock recovery gets more difficult. Such adaptations and redesigns are expensive.